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As we enter the era of customized computing, where customized domain-specific accelerators (DSAs) are used extensively for performance and energy efficiency. Ideally, we would like to enable every programmer should offload the compute-intensive portion of his/her program to one or a set of DSAs, either pre-implemented in ASICs or synthesized on demand on programmable fabrics, such as FPGAs. But integrated circuit (IC) designs remain a black art to many.
High-level synthesis (HLS) made an important progress in simplify IC designs, but it still requires the programmer to provide various pragmas, such as loop unroll, pipelining, and tiling, to define the microarchitecture of the accelerator, which is a challenging task to most software programmer.
In this talk, we present our latest research on automated accelerator synthesis and customized computing on FPGAs, ranging from microarchitecture guided optimization, such as automated generation of highly optimized systolic arrays and stencil computation engines, to more general source-to-source transformation based on graph-based neural networks and meta learning, and finally to latency-insensitive system-level integration.
Alumni, Faculty, General Public, Researchers / Postdocs, Staff, Undergraduate Students, Harvard Community, SEAS Community
Speakers and Presenters
Jason Cong, Distinguished Professor, UCLA Computer Science Department
Organizer
Harvard John A. Paulson School of Engineering and Applied Sciences
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